1. Field of the Invention
This invention relates to a semiconductor device such as a semiconductor diode and its manufacturing method.
2. Description of the Related Art
A voltage regulator diode (a semiconductor diode) 1 shown in FIG. 1 is known. The semiconductor diode (hereinafter referred as xe2x80x9can earlier semiconductor diodexe2x80x9d) 1 has, e.g. a simple three-layer structure stacked in such a way that an n-type semiconductor layer 2 having high impurity concentration, an n-type semiconductor layer 3 and a p-type semiconductor layer 4 having high impurity concentration are stacked sequentially on a silicon substrate. Metal films 5 and 6 to make electrodes are respectively formed on main surfaces of the n-type semiconductor layer 2 and the p-type semiconductor layer 4.
There exists usually a strong electric field in a depletion layer of a pn junction applied of reverse bias voltage for the earlier semiconductor diode 1 having the above junction structure and the electric field gets stronger locally and susceptible to occur breakdown under influence of impurity elements and ions attached on its surface at a chip side where end portions of the pn junction emerge. Therefore, it can often be hard to gain a reverse breakdown voltage expected theoretically for the earlier semiconductor diode 1. To reduce the electric field on the chip side, the bevel contour to machine aslant by an appropriate angle to the pn junction interface 9 for reducing the electric field is adopted. By adopting such the bevel contour, the electric field at the chip outer-surface 7 is reduced and breakdown over the whole face of the junction inside the semiconductor is made to occur to stabilize the breakdown behavior. For semiconductor devices having breakdown voltage higher than the voltage regulator diode, it is known that the breakdown voltage can be improved by adopting the bevel structure.
The earlier semiconductor diode 1, however, has problems as explained below:
(a) For the earlier semiconductor diode 1, to protect the chip outer-surface 7 from the effects of outside environment in an assembling process the chip outer-surface 7 is coated with an insulation film 8 as shown in FIG. 1 after employing wet cleaning by acid or alkali chemicals. However, for the semiconductor diode manufactured in such a way, it is pointed out from the result of product evaluation tests that performance and quality of the product is not stable. The reasons for instability in the performance are given that changes in the surface state and surface failure occur on the chip outer-surface 7 under influence of the wet cleaning or coating of the insulation film 8. Since the surface state of actual semiconductor chips is very active, it is very difficult to control the precision and reproducibility of such surface state.
(b) The earlier semiconductor diode 1 has the n-type semiconductor layer 3 having impurity concentration much lower than that of the p-type semiconductor layer 4, and in the case that it can be considered a one-sided abrupt junction, avalanche breakdown voltage at the pn junction part of the n-type semiconductor layer 3 with the p-type semiconductor layer 4 is determined by impurity concentration of the n-type semiconductor layer 3. Accordingly, it was required to control highly accurately resistivity xcfx81 of a semiconductor (silicon) wafer to be used for a product. This means that a semiconductor wafer regulated in a strict specification for the resistivity xcfx81 was required to be manufactured by a semiconductor wafer manufacturer under a special order and tested after the delivery. In the past, silicon wafers with a narrow range of 0.01 to 0.03 xcexa9xc2x7cm in resistivity xcfx81xe2x80x94for the n-type silicon, it corresponds with a range of 5xc3x971018/cm3 to 7xc3x971017/cm3 in impurity concentrationxe2x80x94were used for the order specification.
(c) For manufacturing of the earlier semiconductor diode 1, since the chip outer-surface 7 has the bevel structure formed aslant to the pn junction interface, there is a problem that the number of processes required increases since processes such as sandblasting, grinding, polishing or etching are added in order to form the bevel structure.
(d) For the earlier semiconductor diode 1, since the chips cut from the semiconductor wafer are in a packed state and have its side face inclined aslant to the front and back surfaces of the chips, the device geometry makes it difficult to mount the chip on a jig such as collet in an assembling process.
In view of these situations, it is an object of the present invention to provide a semiconductor device having a desired stable breakdown voltage, preventing occurrence of a local breakdown on a semiconductor (chip) side face where the pn junction emerges.
More specifically, the present invention would provide a semiconductor device and its manufacturing method capable of extending a range of resistivity xcfx81 of the semiconductor wafer to be originally prepared for manufacturing and lowering cost for the semiconductor wafer.
Another object of the present invention is to provide a manufacturing method for semiconductor device capable of simplifying or omitting chip surface treatment.
Still another object of the present invention is to provide a semiconductor device and its manufacturing method capable of simplifying production process.
Yet still another object of the present invention is to provide a semiconductor device allowing for favorable handling and favorable loading of the chip into a jig, such as the collet, during the product assembly process.
To achieve the above-mentioned objects, the first aspect of the present invention inheres in a semiconductor device embracing (a) a first semiconductor region of a first conductivity type, defined by a first end surface, a second end surface opposing to the first end surface and a first outer surface connecting the first and second end surfaces; (b) a second semiconductor region of the second conductivity type, defined by a third end surface, a fourth end surface opposing to the third end surface and a second outer surface connecting the third and fourth end surfaces, the fourth end surface is in contact with the first end surface; (c) a third semiconductor region of the first conductivity type connected with the first semiconductor region at the second end surface; (d) a fourth semiconductor region of the second conductivity type connected with the second semiconductor region at the third end surface; and (e) a fifth semiconductor region having inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, configured such that the fifth semiconductor region surrounds the first and second semiconductor regions, the fifth semiconductor region is disposed between the third and fourth semiconductor regions. Here, the first conductivity type and the second conductivity type are conductivity types opposite to each other. That is, the second conductivity type is the p-type if the first conductivity type is assigned to be n-type and the second conductivity type is n-type if the first conductivity type is p-type.
According to the semiconductor device of the first aspect of the present invention, the first and the second semiconductor regions are stacked with each other in such a way that they implement a localized pn junction interface (hereinafter referred as xe2x80x9cfirst pn junction interfacexe2x80x9d). Another pn junction interface (hereinafter referred as xe2x80x9csecond pn junction interfacexe2x80x9d) is formed between the fourth semiconductor region and the fifth semiconductor region. Since the impurity concentration of the first semiconductor region is higher than that of the fifth semiconductor region, the first pn junction interface is more susceptible to cause breakdown than the second pn junction interface positioned on the peripheral side of the semiconductor device. Accordingly, since the electrical field on a chip outer-surface of the semiconductor device is relatively reduced so that breakdown occurs at the junction interface inside the semiconductor device, the breakdown behavior can be stabilized. The methodology for stabilizing the breakdown behavior in such a way is effective also in a power semiconductor device having the maximum operation voltage higher than the voltage regulator diode for example.
In the first aspect of the present invention, the outer surface of the fifth semiconductor region can serve as a chip outer-surface of the semiconductor device to make the chip outer-surface substantially perpendicular to the second end surface of the first semiconductor region. That is because the electrical field in the second pn junction interface emerged on the chip outer-surface of the semiconductor device is reduced and less changes are made in breakdown voltage of the semiconductor device even when a change in surface state of the chip outer-surface of the semiconductor device and small surface failures occur. Hence, the beveled junction termination architecture is not required. That is, since the breakdown occurs at the first pn junction interface part deep inside the semiconductor device without adopting the bevel contour at the chip outer-surface of the semiconductor device, the breakdown behavior can be stabilized. Therefore, the outer-surface of the semiconductor device can be cut, or diced using conventional diamond blades. Additionally, the outer-surface of the semiconductor device can be formed so that it is perpendicular to the first main surface of the semiconductor substrate, resulting in improved handling of the semiconductor device (chip).
In the first aspect of the present invention, it is preferable that the fifth region is a semiconductor substrate made of wafer cut from bulk crystal such as an FZ method, a CZ method, and an MCZ method. If impurity concentration of the first semiconductor region is much lower than the second semiconductor region and the localized first pn junction between the first semiconductor region with the second semiconductor region can be considered a one-sided abrupt junction, the avalanche breakdown voltage of the localized first pn junction is determined by impurity concentration of the first semiconductor region independently from the impurity concentration of the fifth semiconductor region. And if it is a double-sided abrupt junction, the avalanche breakdown voltage of the localized first pn junction is determined by impurity concentrations of both the first and the second semiconductor regions independently from the impurity concentration of the fifth semiconductor region. Accordingly, since the impurity concentration of the fifth semiconductor region can be regulated as the original (initial) impurity concentration of the semiconductor substrate used as a raw material, it is not required to prescribe strictly the impurity concentration of the substrate and hence a selection range of the semiconductor substrate to be used can be extended. There is no need to order a semiconductor substrate (wafer) with special specifications and it enables users to lower the cost and shorten the time required to purchase the semiconductor substrate (wafer) as the raw material.
In the first aspect of the present invention, it is preferable that the first main electrode layer is formed on the bottom surface of the third semiconductor region and that the second main electrode is formed on the top surface of the fourth semiconductor region. Operation regions to serve as a current path for a main current of the semiconductor element are defined between the first main electrode layer and the second main electrode layer. The xe2x80x9cfirst main electrode layerxe2x80x9d can be identified as either an anode electrode layer or a cathode electrode in a semiconductor diode and a thyristor. The thyristor can be a GTO thyristor and an static induction thyristor (SI thyristor). If the third semiconductor region is assigned to be the n-type, the first main electrode is the cathode electrode layer. The xe2x80x9csecond main electrode layerxe2x80x9d can be identified as either a cathode electrode layer or an anode electrode layer not being assigned as the first main electrode layer in the semiconductor diode and the thyristor. If the fourth semiconductor region is assigned to be the p-type, the second main electrode is identified as the anode electrode layer. As a result, the third semiconductor region serves as the xe2x80x9cfirst main electrode regionxe2x80x9d being contacted with first main electrode layer, and the fourth semiconductor region serves as the xe2x80x9csecond main electrode regionxe2x80x9d being contacted with second main electrode layer.
Furthermore, the xe2x80x9cfirst main electrode layerxe2x80x9d can be identified as either an emitter electrode layer or a collector electrode layer in a bipolar transistor (BJT) or an IGBT. The bipolar transistor can be an ultra high-frequency transistor that operates in microwave band, millimeter wave band or sub-millimeter wave band such as a heterojunction bipolar transistor (HBT). The present invention can also be applied to an IGFET such as an MOSFET, an MOSSIT or a high electron mobility transistor (HEMT). For the IGFET, the xe2x80x9cfirst main electrode layerxe2x80x9d can be identified as either a source electrode layer or a drain electrode layer. The xe2x80x9csecond main electrode layerxe2x80x9d can be identified as either an emitter electrode layer or a collector electrode that will not be assigned as the first main electrode layer for the BJT and the IGBT, and either a source electrode layer or a drain electrode layer, which will not become the first main electrode layer for the IGFET. For the BJT, the IGBT and the IGFET, a control layer such as a base electrode layer or a gate electrode layer is naturally added.
The second aspect of the present invention inheres in a semiconductor device embracing (a) a first semiconductor region of a first conductivity type, defined by a first end surface, a second end surface opposing to the first end surface and a first outer surface connecting the first and second end surfaces; (b) a second semiconductor region of the second conductivity type, defined by a third end surface, a fourth end surface opposing to the third end surface and a second outer surface connecting the third and fourth end surfaces, the fourth end surface is in contact with the first end surface; (c) a third semiconductor region of the first conductivity type connected with the first semiconductor region at the second end surface; (d) a fourth semiconductor region of the second conductivity type connected with an upper part of the second outer surface near the third end surface; and (e) a fifth semiconductor region having inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, configured such that the fifth semiconductor region surrounds the first and second semiconductor regions, the fifth semiconductor region is disposed between the third and fourth semiconductor regions.
Similar to the first aspect, in the semiconductor device of the second aspect of the present invention, the first semiconductor region and the second semiconductor region are stacked with each other in such a way that they implement the localized first pn junction interface. The second pn junction interface is formed between the fourth semiconductor region and the fifth semiconductor region. Since the impurity concentration of the first semiconductor region is higher than that of the fifth semiconductor region, the first pn junction interface is more susceptible to cause breakdown than the second pn junction interface positioned on the peripheral side of the semiconductor device. Accordingly, since the electrical field on a chip outer-surface of the semiconductor device is relatively reduced so that breakdown occurs at the junction interface inside the semiconductor device, the breakdown behavior can be stabilized.
The third aspect of the present invention inheres in a method of manufacturing a semiconductor device embracing (a) preparing a semiconductor substrate defined by a first main surface a second main surface opposing to the first main surface; (b) forming a first semiconductor region by selectively doping first conductivity type impurity elements through a first diffusion window disposed on the second main surface to a predetermined diffusion depth; (c) forming a second semiconductor region so as to form a pn junction with the first semiconductor region, by selectively doping second conductivity type impurity elements through a second diffusion window having area larger than the first diffusion window, the second diffusion window disposed on the second main surface; (d) forming a third semiconductor region by doping the first conductivity type impurity elements through entire first main surface; and (e) forming a fourth semiconductor region by doping the second conductivity type impurity elements through entire second main surface.
According to the third aspect of the present invention, the first semiconductor and the second semiconductor regions can be formed inside the semiconductor substrate by doping selectively the impurity elements from the second main surface of the semiconductor substrate. The second pn junction interface formed by the fifth semiconductor region and the fourth semiconductor region emerges on a chip outer-surface of the semiconductor device. Since the impurity concentration of the first semiconductor region implementing the first pn junction interface has impurity concentration higher than that of the first conductivity type fifth semiconductor region, breakdown will occur in the first pn junction interface earlier to the second pn junction interface. The breakdown behavior can be stabilized by reducing an electrical field at the chip outer-surface of the semiconductor device in such a way to induce breakdown at the junction part deep inside the semiconductor device. And since the fifth semiconductor region can be used as the original impurity concentration of the semiconductor substrate by adjusting the impurity concentration of the first semiconductor region, it is not required to prescribe strictly the impurity concentration of the substrate and hence a selection range of the semiconductor substrate to be used can be extended.
The fourth aspect of the present invention inheres in a method of manufacturing a semiconductor device embracing (a) preparing a semiconductor substrate defined by a first main surface a second main surface opposing to the first main surface; (b) forming a first semiconductor region by selectively doping first conductivity type impurity elements through a first diffusion window disposed on the first main surface to a predetermined diffusion depth; (c) forming a second semiconductor region so as to form a pn junction with the first semiconductor region, by selectively doping second conductivity type impurity elements through a second diffusion window disposed on the second main surface; (d) forming a third semiconductor region by doping the first conductivity type impurity elements through entire first main surface; and (e) forming a fourth semiconductor region by doping the second conductivity type impurity elements through entire second main surface. Here, whichever can be employed in first of the process sequence to form either the first semiconductor region or the second semiconductor region. And whichever can be employed in first of the process sequence to form either the third semiconductor region or the fourth semiconductor region.
According to the fourth aspect of the present invention, the fourth and the second semiconductor regions are diffused into the semiconductor substrate along mutually opposite directions. Therefore, there will be no problem such as the compensation of the first and second conductivity type impurity elements, and the first and second conductivity type impurity concentrations of each semiconductor regions are easily controlled compared to the semiconductor device manufactured by the method of the third aspect.
The fifth aspect of the present invention inheres in a method of manufacturing a semiconductor device embracing (a) preparing a semiconductor substrate defined by a first main surface a second main surface opposing to the first main surface; (b) forming a third semiconductor region by doping first conductivity type impurity elements through entire first main surface; (c) forming a fourth semiconductor region by doping the second conductivity type impurity elements through entire second main surface; (d) forming a first diffusion trench penetrating through the third semiconductor region from a part of the first main surface; (e) forming a second diffusion trench penetrating through the fourth semiconductor region from a part of the second main surface; (f) forming a first semiconductor region by doping selectively the first conductivity type impurity elements from inner wall and bottom of the first diffusion trench, and (g) forming a second semiconductor region by doping selectively the second conductivity type impurity elements from inner wall and bottom of the second diffusion trench. Here, whichever can be employed in first of the process sequence to form either the first semiconductor region or the second semiconductor region. And whichever can be employed in first of the process sequence to form either the first diffusion trench or the second diffusion trench. Furthermore, whichever can be employed in first of the process sequence to form either the third semiconductor region the fourth semiconductor region. And furthermore, processes to form the third semiconductor region and the fourth semiconductor region can be employed after processes to form the first semiconductor region and the second semiconductor region.
In the fifth aspect of the present invention, since the first and the second semiconductor regions are formed in the semiconductor substrate via the first and the second diffusion trenches, high temperature and long time thermal diffusion treatments are not needed and leads to productivity improvement. Crystal defect resulting from the high temperature and long time thermal diffusion treatment will not occur. Since relatively shallow diffusion is required compared with the methods of third and fourth aspects, impurity concentrations of the first semiconductor region and the second semiconductor region can be easily controlled. And by forming the first main electrode plug and the second main electrode plug with materials having high electric conductivity inside the first and the second diffusion trenches, influence of parasitic resistance can be reduced to provide a voltage regulator diode with higher accuracy. In particular, since the metal electrode layers can contact with the semiconductor regions in wide areas, the contact resistances at the ohmic contacts can be lowered.
In the third through fifth aspects of the present invention, it is preferable to manufacture many semiconductor devices simultaneously on a semiconductor wafer, or on the semiconductor substrate, after dividing the semiconductor wafer by cutting with planes substantially perpendicular to the first main surface so as to obtain many semiconductor chips. In this case, each chip can be stored and carried in a state being stuck to synthetic resin sheet by sticking the synthetic resin sheet to whichever main surface side of the semiconductor substrate to cut the chip so that the synthetic resin sheet is not cut. When packaged and assembled into the product, the semiconductor device in a state of being a chip, which is stuck to the synthetic resin sheet, can be used. Hence, it enables easy handling. Furthermore, since the outer-surface of the semiconductor device (semiconductor chip) is perpendicular to the first main surface of the semiconductor substrate, handling by a jig such as a collet will also be easy.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the present invention in practice.